The present invention relates to a method and apparatus for testing a semiconductor integrated circuit and more particularly to a technique for testing the integrated circuit through probe lines and sense lines, which are incorporated in the integrated circuit so as to intersect (but be electrically separated from) each other at right angles.
In general, the known Scan-Path method and the Cross-Check method have been employed to test whether a large number of logic elements (logic gates) incorporated in an integrated circuit function normally or not.
In the Scan-Path method, test pattern signals are applied in sequence to an integrated circuit, and then output pattern signals from the integrated circuit are observed to detect faults of the logic elements.
Recently, the number of logic elements incorporated in integrated circuits has been increasing rapidly due to the continuing progress of integration technology, so that the testing cost of the Scan-Path method has become expensive because it requires long test time and much labor. In addition, this method requires a large number of flip-flops to be incorporated in the integrated circuit.
Japanese Patent Laid-open Publication No. 1-179,338 discloses a technique for testing an integrated circuit by the Cross-Check method. In this testing technique, as shown in FIG. 8 as an example, a large number of probe lines P.sub.i, P.sub.i+1, P.sub.i+2, each of which corresponds to each row of an array of logic elements such as NAND, NOR, INVERTER, and D-F/F, and a large number of sense lines S.sub.j, S.sub.j+1, S.sub.j+2, each of which corresponds to each column of an array of logic elements, are incorporated in the integrated circuit so as to intersect each other at right angles, and each logic element is disposed so as to correspond to one of intersections where the probe lines P.sub.i, P.sub.i+1, P.sub.i+2 and the sense lines S.sub.j, S.sub.j+1, S.sub.j+2 intersect each other.
A test point TP of each logic element is connected to its corresponding sense line through an electronic switch EQ consisting of a MOSFET, and each electronic switch EQ is turned ON by applying a selection signal to the corresponding probe line.
For example, in a state of one of test pattern signals being applied to the integrated circuit by applying a selection signal of "one" level to the probe line P.sub.i, the electronic switches EQ connected to the probe line P.sub.i are turned ON, and then test signals at the test points TP of an INVERTER, NAND, NOR, etc., are fed to the sense lines S.sub.j, S.sub.j+1, S.sub.j+2, respectively. Next, by applying the selection signal to the probe line P.sub.i+1, test signals at the test points TP of NOR, D-F/F, etc., are fed to the sense lines S.sub.j, S.sub.j+1, S.sub.j+2, respectively. In this manner, by applying the selection signal to the other probe lines in sequence, all logic elements are tested with regard to the one of test pattern signals. Then, another test pattern signal is applied to the integrated circuit, and the same steps as above-described are carried out, and by applying all test pattern signals in sequence to the integrated circuit, all logic elements are tested with regard to all test patterns signals.
It is to be noted that the above-described testing technique requires a large number of probe lines to be incorporated and sense lines in an integrated circuit so that test points correspond, respectively, to intersections where probe lines and sense lines intersect. In other words, if a matrix structure of logic elements, or a matrix structure of test points, consists of X rows and Y columns, it is required to incorporate X probe lines and Y sense lines in an integrated circuit. In order to incorporate such a large number of probe lines and sense lines, integration density of the integrated circuit has to be undesirably reduced; therefore, testing apparatus according to this testing technique can not be practical and economical.